LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PC is
port (
		clk : IN STD_LOGIC;
		Reset : IN STD_LOGIC; 
		LOAD_PC : IN STD_LOGIC; --LOAD_PC和INCR_PC初始化为0保证第一次时钟到来的时候
		INCR_PC : IN STD_LOGIC;
		Addr_Val_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		PC_out : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)
		
);
end PC;

ARCHITECTURE accu OF PC IS

BEGIN

	PROCESS(clk,Reset,LOAD_PC,INCR_PC)
		BEGIN
		IF Reset = '0' THEN
			PC_out <= X"0000";
			ELSIF clk'event AND clk = '1' THEN --信号名'EVENT AND 信号名='1' 功能是检测上升沿
					IF LOAD_PC = '0' AND INCR_PC = '1' THEN
						PC_out <= PC_out + X"0001"; --X"01"为表示16进制，即pc+1
						ELSIF LOAD_PC = '1' THEN --执行jump
						PC_out <= ADDr_Val_in;
						ELSIF LOAD_PC = '0'AND INCR_PC = '0' THEN
						PC_out <= X"0000"; -- 保证第一次执行时钟时，读出0地址指令
					END IF;
		END IF;
	END PROCESS;

END accu;

		